IP and Processors for Smart Edge Designs

A unified AI platform from the edge to the datacenter

Wave’s AI IP platform features a unique combination of AI engines for achieving the right balance of flexibility, performance, efficiency and cost.

Tuned to AI use cases

AI networks requiring low latency, high throughput, concurrent and efficient execution.

Scalable AI Performance

Multi-threaded, Multi-core, Multi-cluster CPUs, Multi-tile dataflow cores

AI Platform Design

Complete AI Technology Building Blocks

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MIPS Processor Cores

MIPS offers a comprehensive portfolio of low-power, high-performance 32- and 64-bit processor IP cores, ranging from high-end mobile applications processors to extremely small cores for deeply embedded microcontrollers.

MIPS Architecture

M-Class
I-Class
P-Class
Aptiv Generation
Classic

M-Class Product Family

M-Class cores are ideal for micro-controller and embedded-type applications such as industrial controllers, Internet of Things (IoT), wearables, wireless communications, automotive and storage. M-Class line-up offers both micro-controller (MCU) and microprocessor (MPU) versions. One of the key features of the family includes hardware virtualization that provides a foundation for MIPS multi-domain security leading to the highest level of security for any embedded micro-controller architecture.

M51xx

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DATASHEET

M5100 Datasheet

M5150 Datasheet

SOFTWARE MANUAL

MIPS32® M5100 Processor Core Family Software User’s Manual

MIPS32® M5150 Processor Core Family Software User’s Manual

OTHER DOCS

Using Virtualization to Implement a Scalable Trusted Execution Environment in Secure SoCs

Hardware-assisted Virtualization with the MIPS Virtualization Module

MIPS-VZ Security Features as Compared to ARMv8-M CMSE

M62xx

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DATASHEET

M6200 Datasheet

M6250 Datasheet

PROGRAMMERS GUIDE

M6200 Programmers Guide

M6250 Programmers Guide

I-Class Product Family

MIPS 32-bit/64-bit I-Class cores are designed for the next generation of high-performance wireless communications, networking, automotive and AI applications. I-Class cores provide highly efficient, scalable, parallel processing performance, designed upon a foundation of hardware multi-threading and multi-core cluster CPU technologies. The latest MIPS I-class core also implements the I7200 nanoMIPS™ instruction set architecture (ISA), a new version of MIPS ISA designed to deliver best in class small code size without sacrificing performance.

I7200

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MIPS I7200 Multiprocessing System Datasheet

MIPS I7200 Multiprocessing System Programmer’s Guide

I6500-F

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MIPS I6500-F Flyer

I6500

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I6400

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P-Class Product Family

MIPS P-Class family, which ranges on the high-end of the MIPS performance spectrum, is being used for connected consumer electronics, supercomputer and HPC applications. The MIPS P-class CPU is based on a wide issue, deeply out-of-order (OoO) implementation, supporting up to six cores in a single cluster with high performance cache coherency. Complementing this raw horsepower, the P-Class family of cores includes a 128-bit integer and floating point SIMD processor, hardware virtualization, and larger physical and virtual addressing capabilities.

P-Class P5600

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P5600 Multiprocessing System Datasheet

P5600 Multiprocessing System Software User’s Manual

P-Class P6600

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MIPS Aptiv Cores

MIPS microAptiv is the smallest, lowest-power CPU family available. The microAptiv cores also have higher performance than competing converged microcontroller/DSP solutions in their class.

MIPS interAptiv is a family of multi-core, multi-threaded 32-bit processors. The MIPS interAptiv CPU family of processors gives designers access to two virtual processing elements (VPEs), or hardware threads, which appear as two complete processors within a symmetric multiprocessing (SMP) operating system.

proAptiv CPUs are based on a wide issue, deeply out-of-order (OoO) implementation of the MIPS32 architecture and are available in single or multi-core product versions supporting up to six cores.

microAptiv

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DATASHEET

microAptiv UC Data Sheet

microAptiv UP Data Sheet

SOFTWARE MANUAL

MIPS32 microAptiv UP Processor Core Family Software Users Manual

MIPS32 microAptiv UC Processor Core Family Software Users Manual

OTHER DOCS

The Convergence of MCU/MPU and DSP

interAptiv

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MIPS32® interAptiv Multiprocessing System Datasheet

MIPS32® interAptiv Multiprocessing System Software User’s Manual

proAptiv

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MIPS Classic Cores

MIPS Classic Cores target every level of performance needed to support any embedded use case from entry-level to high-performance — whether it be digital consumer, broadband access and networking, or state-of-the-art communications.

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